(1) Field of the Invention
The disclosure relates to a multi-port bridge device in a computer system, and more particularly relates to the bridge device having at least one accelerated graphic port (AGP) and a peripheral component interconnect (PCI) port and a computer system therefor.
(2) Description of the Prior Art
FIG. 1 is a block diagram of a typical computer system supporting both accelerated graphic port (AGP) and peripheral component interconnect (PCI) interface. The computer system 100 has a central processing unit (CPU) 110, a core logic 120, a random access memory (RAM) 130, an AGP bus 152, a PCI bus 142, a PCI/PCI bridge 140, an AGP interface device 150, and at least one PCI interface device 160, and for example, three PCI interface devices 160 are shown in FIG. 1.
The CPU 110 is electrically connected to the core logic 120 through a host bus 112. The RAM 130 is electrically connected to the core logic 120 through a memory bus 132. The AGP interface device 150 is electrically connected to the core logic 120 through the AGP bus 152. The PCI/PCI bridge 140 is electrically connected to the core logic 120 through the PCI bus 142. The PCI interface devices 160 are electrically connected to the PCI/PCI bridge 140 and further electrically connected to the core logic 120 through the PCI bus 142.
FIG. 2 is a functional block diagram of the core logic 120 in FIG. 1. As shown, the core logic 120 has a host bus interface 122, a memory bus interface 124, and a host/PCI bridge 126. The host bus interface 122 is electrically connected to the host bus 112 for accessing data, address, and control signals from the CPU 110. In addition, the host bus interface 122 is also electrically connected to the memory bus interface 124 and the host/PCI bridge 126. The memory bus interface 124 is electrically connected to the memory bus 132 and generates control signals and timing signals for deciding reading and writing procedures within the memory 130. The host/PCI bridge 126 is electrically connected to the PCI bus 142 and the AGP bus 152.
Ordinarily, AGP interface was developed on the basis of PCI interface but focusing on upgrading the bandwidth between the graphic accelerator and the memory to meet the demand of huge data transmission due to 3-dimensional images. Table. 1 lists the differences between AGP interface and PCI interface. As shown, not only the type of connectors but also the data transmission philosophy of the two interfaces are different.
InterfaceAGPPCIOperation speed32 Bits32 BitsOperation frequency66 MHz33/66 MHz(usually 33 MHz)No. of contacts132 double layer (4X)120 single layer124 double layer (8X)ExecutionPipelined RequestsNon-pipelinedAddress/DataAddress/Data de-Address/DatatransmissionmultiplexedmultiplexedTransmission speed1066 MB/s (4X)133 MB/s (33 MHz)2133 MB/s (8X)
Since the transmission speed available by using AGP interface is much greater than that by using PCI interface, the AGP bus 152 of FIG. 1 supports a bandwidth much greater than the PCI bus 142 does. Furthermore, since the three PCI interface devices 160 electrically connected to the PCI/PCI bridge 140 are electrically connected to the 15 core logic 120 through the PCI bus 142 in present, the bandwidth of the PCI bus 142 has to be shared by the three PCI interface devices 160 simultaneously.
As mentioned, the operation speed and efficiency of the PCI interface devices 160 are very much restricted by the bandwidth of the PCI bus 142. Therefore, for the improvement of the operation of the whole computer system, it has become an important issue to break through the limitation of the bandwidth of the PCI bus.